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Rama Krishna, T. V.
- Performance of a Microstrip-Fed Patch and Probe-Fed Patch Antenna
Abstract Views :163 |
PDF Views:4
Authors
Affiliations
1 ECE Department, K L University, IN
2 ECE Department, K L University, Vaddeswaram, Guntur, Andhra Pradesh, IN
1 ECE Department, K L University, IN
2 ECE Department, K L University, Vaddeswaram, Guntur, Andhra Pradesh, IN
Source
Wireless Communication, Vol 4, No 15 (2012), Pagination: 866-868Abstract
This paper describes variety of feeding technique applicable to microstrip patch antenna which is one of the important aspects. Probe-fed microstrip patch antennas have always been a popular candidate for a variety of antenna systems. Due to their many salient features, they are well suited for modern wireless communication systems. Details of the antenna simulated results are presented. The probe-fed patch has central frequency 2480 MHz that is about 1% higher than in the experiment [1], the bandwidth of lossless patch is 2.8% (3.1% in the experiment). The microstrip-fed patch has central frequency 2400 MHz that is 2% lower than in the experiment.Keywords
Microstrip Patch Antenna, Feeding Techniques.
- An Effective on-Chip Network Topology for Network on Chip (Noc) Trade-Offs
Abstract Views :179 |
PDF Views:0
Authors
M. Venkateswara Rao
1,
T. V. Rama Krishna
1,
S. Raaga Sai Sruthi
2,
S. Akhila
2,
Y. Gopi
2,
L. Bhavani Krishna
2
Affiliations
1 Department of Electronics and Communications Engineering, K L University, Vaddeswaram, Guntur – 522502, Andhra Pradesh, IN
2 Department of Electronics and Computer Engineering, K L University, Vaddeswaram, Guntur - 522502, Andhra Pradesh, IN
1 Department of Electronics and Communications Engineering, K L University, Vaddeswaram, Guntur – 522502, Andhra Pradesh, IN
2 Department of Electronics and Computer Engineering, K L University, Vaddeswaram, Guntur - 522502, Andhra Pradesh, IN
Source
Indian Journal of Science and Technology, Vol 9, No 17 (2016), Pagination:Abstract
Background/objectives: The major contribution in very large scale integrated circuits is given by System on Chip (SoC) technology. Many fuzzy logics are been implemented on SoC’s and are effectively supported by them. In time the Networks came into existence and interconnection of networks became very necessary so Network on Chips (NoC) was implemented and many topologies were also suggested. The main aim of this paper is to find an effective on-chip topology for network on chips. Methods/Statistical Analysis: Topologies related to this network on chips gives different routing algorithms which defines the direction of the route. Different algorithms were proposed for different topologies defining the direction, traffic rate at which the packet is entering, latency, and throughput. These were considered as the main trade off’s for Network on Chip. Findings: in this paper discussion on 4 topologies was done by taking few main properties into account and implementation of the topologies were done in software. It was found that latency and throughput plays a major role in the topology and along with these 2 the packet rate and flit rate also play a key role. The values of all trade-offs for every topology were taken and graphs were plotted showing the variation between the topologies. The efficiency of each topology can be observed in respective graph. Application/Improvements: Network on chips is used in routers and these can be further improved in to wireless connections.Keywords
Interconnection Networks, Latency, Routing algorithm Throughput, TopologyFull Text